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| LOW NOISE, HIGH LINEARITY PACKAGED PHEMT FPD750SOT343 * PERFORMANCE (1850 MHz) 0.3 dB Noise Figure at 25% Bias 20 dBm Output Power (P1dB) 18 dB Small-Signal Gain (SSG) 38 dBm Output IP3 at 50% Bias Evaluation Boards Available Available in Lead Free Finish: FPD750SOT343E * DESCRIPTION AND APPLICATIONS The FPD750SOT343 is a packaged depletion mode AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (pHEMT). It utilizes a 0.25 m x 750 m Schottky barrier Gate, defined by high-resolution stepper-based photolithography. The recessed and offset Gate structure minimizes parasitics to optimize performance, with an epitaxial structure designed for improved linearity over a range of bias conditions and input power levels. The FPD750 is available in die form and in other packages. Typical applications include drivers or output stages in PCS/Cellular base station high-interceptpoint LNAs, WLL and WLAN systems, and other types of wireless infrastructure systems. * ELECTRICAL SPECIFICATIONS AT 22C Parameter Minimum Noise Figure Output Third-Order Intercept Point (from 15 to 5 dB below P1dB) Small-Signal Gain Power at 1dB Gain Compression SSG P1dB Symbol NF IP3 Test Conditions VDS = 3.3 V; IDS = 50% IDSS VDS = 3.3 V; IDS = 25% IDSS VDS = 3.3 V; IDS = 50% IDSS VDS = 3.3 V; IDS = 25% IDSS Tuned for Optimum IP3 VDS = 3.3 V; IDS = 50% IDSS VDS = 3.3 V; IDS = 25% IDSS VDS = 3.3 V; IDS = 50% IDSS VDS = 3.3 V; IDS = 25% IDSS Saturated Drain-Source Current Maximum Drain-Source Current Transconductance Gate-Source Leakage Current Pinch-Off Voltage Gate-Source Breakdown Voltage Gate-Drain Breakdown Voltage IDSS IMAX GM IGSO |VP| |VBDGS| |VBDGD| VDS = 1.3 V; VGS = 0 V VDS = 1.3 V; VGS +1 V VDS = 1.3 V; VGS = 0 V VGS = -5 V VDS = 1.3 V; IDS = 0.75 mA IGS = 0.75 mA IGD = 0.75 mA 0.7 12 12 185 19 16.5 18 17 20 18 230 375 200 5 1.0 16 18 Revised: 04/28/05 Email: sales@filcsi.com Min Typ 0.6 0.3 Max 0.9 Units dB dBm RF SPECIFICATIONS MEASURED AT f = 1850 MHz USING CW SIGNAL 35.5 38 34 dB dBm 280 mA mA mS A 1.3 V V V Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis LOW NOISE, HIGH LINEARITY PACKAGED PHEMT FPD750SOT343 * ABSOLUTE MAXIMUM RATINGS1 Parameter Drain-Source Voltage Gate-Source Voltage Drain-Source Current Gate Current RF Input Power 2 Symbol VDS VGS IDS IG PIN TCH TSTG PTOT Comp. 3 Test Conditions -3V < VGS < +0V 0V < VDS < +8V For VDS > 2V Forward or reverse current Under any acceptable bias state Under any acceptable bias state Non-Operating Storage See De-Rating Note below Under any bias conditions Min Max 6 -3 IDSS 7.5 175 175 Units V V mA mA mW C C W dB % Channel Operating Temperature Storage Temperature Total Power Dissipation Gain Compression 1 -40 150 1.1 5 Simultaneous Combination of Limits 2 or more Max. Limits 80 2 TAmbient = 22C unless otherwise noted Max. RF Input Limit must be further limited if input VSWR > 2.5:1 3 Users should avoid exceeding 80% of 2 or more Limits simultaneously Notes: * Operating conditions that exceed the Absolute Maximum Ratings will result in permanent damage to the device. * Total Power Dissipation defined as: PTOT (PDC + PIN) - POUT, where: PDC: DC Bias Power PIN: RF Input Power POUT: RF Output Power * Total Power Dissipation to be de-rated as follows above 22C: PTOT= 1.1W - (0.007W/C) x TPACK where TPACK = source tab lead temperature above 22C (coefficient of de-rating formula is the Thermal Conductivity) Example: For a 65C source lead temperature: PTOT = 1.1W - (0.007 x (65 - 22)) = 0.8W * HANDLING PRECAUTIONS To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. These devices should be treated as Class 1A per ESD-STM5.1-1998, Human Body Model. Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263. APPLICATIONS NOTES & DESIGN DATA Applications Notes are available from your local Filtronic Sales Representative or directly from the factory. Complete design data, including S-parameters, noise data, and large-signal models are available on the Filtronic web site. Evaluation Boards available upon request. * Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis Revised: 04/28/05 Email: sales@filcsi.com LOW NOISE, HIGH LINEARITY PACKAGED PHEMT FPD750SOT343 * BIASING GUIDELINES Active bias circuits provide good performance stabilization over variations of operating temperature, but require a larger number of components compared to self-bias or dual-biased. Such circuits should include provisions to ensure that Gate bias is applied before Drain bias, otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for additional information. Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage supply for depletion-mode devices such as the FPD750SOT343. Self-biased circuits employ an RF-bypassed Source resistor to provide the negative Gate-Source bias voltage, and such circuits provide some temperature stabilization for the device. A nominal value for circuit development is 5.45 for a 50% of IDSS operating point. For standard Class A operation, a 50% of IDSS bias point is recommended. A small amount of RF gain expansion prior to the onset of compression is normal for this operating point. Note that pHEMTs, since they are "quasi- E/D mode" devices, exhibit Class AB traits when operated at 50% of IDSS. To achieve a larger separation between P1dB and IP3, an operating point in the 25% to 33% of IDSS range is suggested. Such Class AB operation will not degrade the IP3 performance. PACKAGE OUTLINE (dimensions in mm) * SOURCE GATE DRAIN SOURCE All information and specifications subject to change without notice. Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis Revised: 04/28/05 Email: sales@filcsi.com LOW NOISE, HIGH LINEARITY PACKAGED PHEMT FPD750SOT343 Minimum Noise Figure 2 1.8 1.6 1.4 1.2 FMIN 1 0.8 0.6 0.4 0.2 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Frequency (GHz) 10 9 Output Power (dBm) and 3rd-Order Intermodulation Products (dBc) vs. Input Power -51.00 -53.00 8 Pout (dBm) 7 Pout, (dBm) 6 5 -59.00 4 -61.00 3 2 -14.5 -13.4 -12.3 -11.3 Pin, (dBm) -10.3 -9.3 -8.2 -63.00 -57.00 3rds (dBc) -55.00 3rd-Order IM Products, (dBc) Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis Revised: 04/28/05 Email: sales@filcsi.com |
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